////`default_nettype none   
//synthesis translate_off 
`include "../../timescale.v"  
//synthesis translate_on
`include "../../DSP_define.v"
module tb_PW;
reg                sys_clk;
reg                rst_n;
reg                DSP_core_en; 
reg                Int_Sev; 
reg                FP_en;     
reg[4:0]           PS_PC;
reg[31:0]          Fet_Pkt_i;//fetch packet
reg                Fet_Pkt_rdy;   
reg                DP_stall;
reg                I_FP_invalid;
reg                D_RAM_invalid;
reg                PS_io_invalid; 
wire               PW_io_invalid;  
wire[4:0]          PW_PC;
wire[31:0]         Fet_Pkt_o;     

initial 
    sys_clk=1'b1;
    
always #10 sys_clk = ~sys_clk; 

initial 
begin
//*********************--------assignment 1---------*********************//      
    //simulate 0
      #1                 rst_n=1'b0; 
                         PS_PC=32'b0;
                         Fet_Pkt_i=256'b0;                        
                         Fet_Pkt_rdy=1'b0;  
                         DP_stall=1'b0;
                         I_FP_invalid=1'b0;
                         D_RAM_invalid=1'b0;
                         PS_io_invalid=1'b0;   
                         Int_Sev=1'b0;
      #20 //simulate 1
                         rst_n=1'b1; 
                         PS_PC=32'b1;
                         Fet_Pkt_i=256'b1;                        
                         Fet_Pkt_rdy=1'b0;  
                         DP_stall=1'b0;
                         I_FP_invalid=1'b0;
                         D_RAM_invalid=1'b0;
                         PS_io_invalid=1'b0;   
                         Int_Sev=1'b0;

      #20 //simulate 2
                         rst_n=1'b1; 
                         PS_PC=32'b10;
                         Fet_Pkt_i=256'b10;                        
                         Fet_Pkt_rdy=1'b1;  
                         DP_stall=1'b0;
                         I_FP_invalid=1'b0;
                         D_RAM_invalid=1'b0;
                         PS_io_invalid=1'b0;   
                         Int_Sev=1'b0;
      #20 //simulate 3
                         rst_n=1'b1; 
                         PS_PC=32'b11;
                         Fet_Pkt_i=256'b11;                        
                         Fet_Pkt_rdy=1'b1;  
                         DP_stall=1'b0;
                         I_FP_invalid=1'b0;
                         D_RAM_invalid=1'b0;
                         PS_io_invalid=1'b0;   
                         Int_Sev=1'b0;
      #20 //simulate 4
                         rst_n=1'b1; 
                         PS_PC=32'b100;
                         Fet_Pkt_i=256'b100;                        
                         Fet_Pkt_rdy=1'b1;  
                         DP_stall=1'b1;
                         I_FP_invalid=1'b0;
                         D_RAM_invalid=1'b0;
                         PS_io_invalid=1'b0;   
                         Int_Sev=1'b0;
      #20 //simulate 5
                         rst_n=1'b1; 
                         PS_PC=32'b101;
                         Fet_Pkt_i=256'b101;                        
                         Fet_Pkt_rdy=1'b1;  
                         DP_stall=1'b1;
                         I_FP_invalid=1'b0;
                         D_RAM_invalid=1'b0;
                         PS_io_invalid=1'b1;   
                         Int_Sev=1'b0;
      #20 //simulate 6
                         rst_n=1'b1; 
                         PS_PC=32'b110;
                         Fet_Pkt_i=256'b110;                        
                         Fet_Pkt_rdy=1'b1;  
                         DP_stall=1'b0;
                         I_FP_invalid=1'b0;
                         D_RAM_invalid=1'b0;
                         PS_io_invalid=1'b1;   
                         Int_Sev=1'b1;
      #20 //simulate 7
                         rst_n=1'b1; 
                         PS_PC=32'b111;
                         Fet_Pkt_i=256'b111;                        
                         Fet_Pkt_rdy=1'b1;  
                         DP_stall=1'b0;
                         I_FP_invalid=1'b0;
                         D_RAM_invalid=1'b0;
                         PS_io_invalid=1'b1;   
                         Int_Sev=1'b0;
      #20 //simulate 8
                         rst_n=1'b1; 
                         PS_PC=32'b1000;
                         Fet_Pkt_i=256'b1000;                        
                         Fet_Pkt_rdy=1'b1;  
                         DP_stall=1'b0;
                         I_FP_invalid=1'b0;
                         D_RAM_invalid=1'b0;
                         PS_io_invalid=1'b1;   
                         Int_Sev=1'b0;
      #20 //simulate 9
                         rst_n=1'b1; 
                         PS_PC=32'b1001;
                         Fet_Pkt_i=256'b1001;                        
                         Fet_Pkt_rdy=1'b1;  
                         DP_stall=1'b0;
                         I_FP_invalid=1'b0;
                         D_RAM_invalid=1'b0;
                         PS_io_invalid=1'b1;   
                         Int_Sev=1'b0;
 
       #20 $stop;                                  
end


      

PW     PW_U1(   
             sys_clk,
             rst_n,
             DSP_core_en,
             Int_Sev,  
             FP_en,                            
             PS_PC,
             Fet_Pkt_i,//fetch packet reg                       
             Fet_Pkt_rdy,   
             DP_stall,
             I_FP_invalid,
             D_RAM_invalid,
             PS_io_invalid,
             PW_io_invalid,     
             PW_PC,
             Fet_Pkt_o//fetch packet wire                                                                                     
             );

 
endmodule





   

